Performance of semiconductor devices may be enhanced by increasing carrier (electron or hole) mobility in some semiconductor devices such as a metal oxide semiconductor field effect transistor (MOSFET). When stress is applied to the channel of a semiconductor transistor, the mobility of carriers, and as a consequence, the transconductance and the on-current of the transistor are altered from their original values for an unstressed semiconductor. This is because the applied stress and the resulting strain on the semiconductor structure within the channel affects the band gap structure (i.e., breaks the degeneracy of the band structure) and changes the effective mass of carriers. The effect of the stress depends on the crystallographic orientation of the plane of the channel, the direction of the channel within the crystallographic orientation, and the direction of the applied stress. Manipulating stress is an effective way of improving the minority carrier mobility in a MOSFET and increasing the transconductance (or reduced serial resistance) of the MOSFET that requires relatively small modifications to semiconductor processing while providing significant enhancement to MOSFET performance.
The effect of a stress on conductivity of a material is in general called the “piezoresistance effect.” Semiconductor materials typically display a piezoresistive effect since the stress induces strain, which in turn changes the band structure of the semiconductor material. The piezoresistance effect depends on the composition of the semiconductor material, doping type of the semiconductor material, direction of the current flow relative to the crystallographic axes of the semiconductor material, direction and magnitude of the applied stress, and the temperature of the semiconductor material. Quantitative analysis of the piezoresistance effect on silicon is disclosed in Y. Kanda, “A Graphical Representation of the Piezoresistance Coefficients in Silicon,” IEEE Transactions on Electron Devices, Vol. ED-29, pp. 64-70, No. 1, Jan. (1982), which is herein incorporated by reference.
For a block of semiconductor material, using [100], [010], and [001] axes as a reference frame, the fractional resistivity change A is related to the stress X applied to the block of the semiconductor material through a piezoresistance coefficient matrix Π by the following formula, Δ=ΠX, wherein
      Δ    =          [                                                  Δ              11                                                                          Δ              22                                                                          Δ              33                                                                          Δ              23                                                                          Δ              31                                                                          Δ              12                                          ]        ,      Π    =          [                                                  π              11                                                          π              12                                                          π              12                                            0                                0                                0                                                              π              12                                                          π              11                                                          π              12                                            0                                0                                0                                                              π              12                                                          π              12                                                          π              11                                            0                                0                                0                                                0                                0                                0                                              π              44                                            0                                0                                                0                                0                                0                                0                                              π              44                                            0                                                0                                0                                0                                0                                0                                              π              44                                          ]        ,            and      ⁢                          ⁢      X        =          [                                                  σ              11                                                                          σ              22                                                                          σ              33                                                                          σ              23                                                                          σ              31                                                                          σ              12                                          ]        ,and wherein the suffixes 1, 2, and 3 refer to each of the [100], [010], and [001] axes, respectively.
A piezoresistive coefficient, o in the direction of the channel, i.e., in the direction of current flow, of a MOSFET formed in an arbitrary orientation on the block of the semiconductor material may then be calculated. In general, the piezoresistive coefficient, o in the direction of the channel is dependent on the direction of the stress.
To illustrate an example, a p-type MOSFET, i.e., a “PMOSFET” or a “PFET” for short, and an n-type MOSFET, i.e., an “NMOSFET” or an “NFET” for short, formed on a silicon substrate having a surface orientation of (001) is considered. The channel, i.e., the direction of the current flow, is along a [110] crystallographic orientation in this case. A coordinate system having an X-direction along the [110] crystallographic orientation, a Y-direction along a [1 1 0] crystallographic orientation, and a Z-direction along a [001] crystallographic orientation is adopted. The X-Y plane is the plane of the interface between the channel and a gate dielectric. Piezoresistive coefficients along the X, Y, and Z direction, respectively, are tabulated in Table 1.
TABLE 1Piezoresistive coefficients of silicon for uniaxial stress applied alongselected orientations for current flowing along a [110] crystallographicorientation (Unit: 1.0 × 10−12 cm2/dyne)PiezoresistiveCrystallographiccoefficientPiezoresistive coefficientDirectionorientationfor a PFETfor an NFETX[110]−31.6 × 10−12  71.8 × 10−12 cm2/dynecm2/dyneY[1 10]−17.6 × 10−12 −66.3 × 10−12 cm2/dynecm2/dyneZ[001] 53.5 × 10−12  −1.1 × 10−12 cm2/dynecm2/dyne
A uniaxial stress along the direction of the channel, i.e., along the X-direction, is herein referred to as a longitudinal stress, while a uniaxial stress along the direction perpendicular to the direction of the channel and within the plane of the channel, i.e., along the Y-direction, is herein referred to as a transverse stress. A uniaxial stress along the direction perpendicular to the plane of the channel, i.e., along the Z-direction, is herein referred to as a vertical stress. Since the mobility of charge carriers is proportional to the conductivity, which is inversely proportional to the resistivity, the performance of a PFET formed on a (001) silicon substrate and having a channel along a [110] crystallographic orientation, as measured by its on-current, increases under a compressive longitudinal stress, a tensile transverse stress, and/or a tensile vertical stress. The performance of an NFET formed on a (001) silicon substrate and having a channel along a [110] crystallographic orientation, as measured by its on-current, increases under a tensile longitudinal stress, a tensile transverse stress, and/or a compressive vertical stress. Thus, a tensile transverse improves performance of the PFET and the NFET if each is formed on a (001) silicon substrate and has a channel along a [110] crystallographic orientation. However, applying such a tensile stress along a longitudinal direction would produce an advantageous effect in the case of the NFET, while producing a disadvantageous effect in the case of the PFET.
Selection of different materials and different crystallographic orientations may generate different responses for various semiconductor devices in general. In many of these cases, a uniaxial stress present in one direction within the plane of the surface of a semiconductor substrate may confer performance enhancement to both a PFET and an NFET. In other words, the PFET and the NFET may be placed such that a uniaxial transverse stress enhances performance of the PFET and the NFET. Such uniaxial transverse stress may be compressive or tensile.
In view of the above, there exists a need for semiconductor structures for applying a uniaxial stress anisotropically on semiconductor devices such that the uniaxial stress is applied predominantly in one direction and not in another direction.
Further, there exists a need for semiconductor structures comprising a transistor in which an applied stress is predominantly a uniaxial transverse stress.
Yet further, there exists a need for semiconductor structures comprising a PFET and an NFET, each having an applied stress that is predominantly a uniaxial transverse stress.